clockgen Project Status (12/07/2010 - 12:31:28)
Project File: clockgen.xise Parser Errors: No Errors
Module Name: clockgen Implementation State: Fitted
Target Device: xc9536xl-5VQ44
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
4 Warnings (4 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue 7. Dec 12:31:15 201004 Warnings (4 new)0
Translation ReportCurrentTue 7. Dec 12:31:18 2010000
CPLD Fitter Report (Text)CurrentTue 7. Dec 12:31:21 201001 Warning (1 new)1 Info (1 new)
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 12/07/2010 - 12:31:29