Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
941 |
30,064 |
3% |
|
Number used as Flip Flops |
940 |
|
|
|
Number used as Latches |
1 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
0 |
|
|
|
Number of Slice LUTs |
1,172 |
15,032 |
7% |
|
Number used as logic |
1,029 |
15,032 |
6% |
|
Number using O6 output only |
694 |
|
|
|
Number using O5 output only |
158 |
|
|
|
Number using O5 and O6 |
177 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
94 |
3,664 |
2% |
|
Number used as Dual Port RAM |
0 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
94 |
|
|
|
Number using O6 output only |
76 |
|
|
|
Number using O5 output only |
2 |
|
|
|
Number using O5 and O6 |
16 |
|
|
|
Number used exclusively as route-thrus |
49 |
|
|
|
Number with same-slice register load |
35 |
|
|
|
Number with same-slice carry load |
14 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
523 |
3,758 |
13% |
|
Number of MUXCYs used |
340 |
7,516 |
4% |
|
Number of LUT Flip Flop pairs used |
1,449 |
|
|
|
Number with an unused Flip Flop |
616 |
1,449 |
42% |
|
Number with an unused LUT |
277 |
1,449 |
19% |
|
Number of fully used LUT-FF pairs |
556 |
1,449 |
38% |
|
Number of unique control sets |
106 |
|
|
|
Number of slice register sites lost to control set restrictions |
453 |
30,064 |
1% |
|
Number of bonded IOBs |
54 |
186 |
29% |
|
Number of LOCed IOBs |
53 |
54 |
98% |
|
Number of RAMB16BWERs |
2 |
52 |
3% |
|
Number of RAMB8BWERs |
1 |
104 |
1% |
|
Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
Number used as BUFIO2s |
1 |
|
|
|
Number used as BUFIO2_2CLKs |
0 |
|
|
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
Number of BUFG/BUFGMUXs |
5 |
16 |
31% |
|
Number used as BUFGs |
1 |
|
|
|
Number used as BUFGMUX |
4 |
|
|
|
Number of DCM/DCM_CLKGENs |
0 |
4 |
0% |
|
Number of ILOGIC2/ISERDES2s |
0 |
272 |
0% |
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
24 |
272 |
8% |
|
Number used as IODELAY2s |
0 |
|
|
|
Number used as IODRP2s |
2 |
|
|
|
Number used as IODRP2_MCBs |
22 |
|
|
|
Number of OLOGIC2/OSERDES2s |
48 |
272 |
17% |
|
Number used as OLOGIC2s |
0 |
|
|
|
Number used as OSERDES2s |
48 |
|
|
|
Number of BSCANs |
1 |
4 |
25% |
|
Number of BUFHs |
0 |
160 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
1 |
4 |
25% |
|
Number of DSP48A1s |
0 |
38 |
0% |
|
Number of ICAPs |
0 |
1 |
0% |
|
Number of MCBs |
1 |
2 |
50% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
2 |
2 |
100% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Number of RPM macros |
13 |
|
|
|
Average Fanout of Non-Clock Nets |
3.25 |
|
|
|