Key_Jitter Project Status (11/14/2019 - 08:43:55) | |||
Project File: | Key_Jitter.xise | Parser Errors: | No Errors |
Module Name: | Key_Jitter | Implementation State: | Programming File Generated |
Target Device: | xc6slx25-2ftg256 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Registers | 0 | 30,064 | 0% | ||
Number of Slice LUTs | 0 | 15,032 | 0% | ||
Number of occupied Slices | 0 | 3,758 | 0% | ||
Number of MUXCYs used | 0 | 7,516 | 0% | ||
Number of LUT Flip Flop pairs used | 0 | ||||
Number of bonded IOBs | 5 | 186 | 2% | ||
Number of LOCed IOBs | 5 | 5 | 100% | ||
IOB Flip Flops | 1 | ||||
Number of RAMB16BWERs | 0 | 52 | 0% | ||
Number of RAMB8BWERs | 0 | 104 | 0% | ||
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% | ||
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% | ||
Number of BUFG/BUFGMUXs | 1 | 16 | 6% | ||
Number used as BUFGs | 1 | ||||
Number used as BUFGMUX | 0 | ||||
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% | ||
Number of ILOGIC2/ISERDES2s | 1 | 272 | 1% | ||
Number used as ILOGIC2s | 1 | ||||
Number used as ISERDES2s | 0 | ||||
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 272 | 0% | ||
Number of OLOGIC2/OSERDES2s | 0 | 272 | 0% | ||
Number of BSCANs | 0 | 4 | 0% | ||
Number of BUFHs | 0 | 160 | 0% | ||
Number of BUFPLLs | 0 | 8 | 0% | ||
Number of BUFPLL_MCBs | 0 | 4 | 0% | ||
Number of DSP48A1s | 0 | 38 | 0% | ||
Number of ICAPs | 0 | 1 | 0% | ||
Number of MCBs | 0 | 2 | 0% | ||
Number of PCILOGICSEs | 0 | 2 | 0% | ||
Number of PLL_ADVs | 0 | 2 | 0% | ||
Number of PMVs | 0 | 1 | 0% | ||
Number of STARTUPs | 0 | 1 | 0% | ||
Number of SUSPEND_SYNCs | 0 | 1 | 0% | ||
Average Fanout of Non-Clock Nets | 0.75 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu Nov 14 08:36:59 2019 | 0 | 0 | 0 | |
Translation Report | Current | Thu Nov 14 08:43:26 2019 | 0 | 0 | 0 | |
Map Report | Current | Thu Nov 14 08:43:34 2019 | 0 | 0 | 6 Infos (0 new) | |
Place and Route Report | Current | Thu Nov 14 08:43:42 2019 | 0 | 0 | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Thu Nov 14 08:43:47 2019 | 0 | 0 | 4 Infos (0 new) | |
Bitgen Report | Current | Thu Nov 14 08:43:54 2019 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | Mon Aug 22 22:38:12 2016 | |
WebTalk Log File | Current | Thu Nov 14 08:43:55 2019 |