Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store non-default values only |
PROP_SelectedInstanceHierarchicalPath=/Key_Jitter_TB |
PROP_Simulator=Modelsim-SE Verilog |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2015-08-12T19:52:14 |
PROP_intWbtProjectID=72D2288FF593401FB51458250AE82308 |
PROP_intWbtProjectIteration=10 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.Key_Jitter_TB |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_DevDevice=xc6slx16 |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=ftg256 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
FILE_VERILOG=1 |