Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT Target Device: xc6slx16
Project ID (random number) 149502f20f3d4a3a9f1106c04d754440.72D2288FF593401FB51458250AE82308.10 Target Package: ftg256
Registration ID __0_0_0 Target Speed: -2
Date Generated 2016-08-22T22:38:11 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i3 CPU M 330 @ 2.13GHz CPU Speed 2128 MHz
OS Name Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i3 CPU M 330 @ 2.13GHz CPU Speed 2128 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Registers=1
  • Flip-Flops=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=5
  • AGG_IO=5
  • AGG_LOCED_IO=5
  • NUM_BONDED_IOB=5
  • NUM_BUFG=1
  • NUM_ILOGIC2=1
  • NUM_IOB_FF=1
  • NUM_LOCED_IOB=5
 		NetStatistics
  • NumNets_Active=10
  • NumNets_Gnd=1
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=1
  • NumNodesOfType_Active_CLKPINFEED=1
  • NumNodesOfType_Active_CNTRLPIN=1
  • NumNodesOfType_Active_GENERIC=6
  • NumNodesOfType_Active_GLOBAL=8
  • NumNodesOfType_Active_INPUT=1
  • NumNodesOfType_Active_IOBIN2OUT=4
  • NumNodesOfType_Active_IOBOUTPUT=3
  • NumNodesOfType_Active_OUTBOUND=4
  • NumNodesOfType_Active_OUTPUT=1
  • NumNodesOfType_Active_PADINPUT=1
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=1
  • NumNodesOfType_Active_PINFEED=5
  • NumNodesOfType_Active_PINFEED2=1
  • NumNodesOfType_Active_SINGLE=3
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_GENERIC=1
  • NumNodesOfType_Gnd_IOBIN2OUT=1
  • NumNodesOfType_Gnd_IOBOUTPUT=1
  • NumNodesOfType_Gnd_OUTBOUND=1
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PADINPUT=1
  • NumNodesOfType_Gnd_PINFEED=1
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=1
  • IOB-IOBS=4
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • HARD0=1
  • ILOGIC2=1
  • ILOGIC2_IFF=1
  • INVERTER=1
  • IOB=5
  • IOB_IMUX=3
  • IOB_INBUF=3
  • IOB_OUTBUF=2
  • PAD=5
  • SELMUX2_1=1
 
Configuration Data
BSCAN_BSCAN
  • JTAG_CHAIN=[1:1]
  • JTAG_TEST=[0:1]
 FF_SR
  • CK=[CK:1] [CK_INV:0]
  • SRINIT=[SRINIT0:1]
  • SYNC_ATTR=[ASYNC:1]
 ILOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:1]
 ILOGIC2_IFF
  • CLK0=[CLK0_INV:0] [CLK0:1]
  • IFFTYPE=[FF:1]
  • SRINIT_Q=[1:1]
  • SRTYPE_Q=[ASYNC:1]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:2]
  • SLEW=[SLOW:2]
  • SUSPEND=[3STATE:2]
 LUT_OR_MEM5
  • CLK=[CLK:23] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:23]
  • RAMMODE=[SRL16:11] [SRL32:12]
 LUT_OR_MEM6
  • CLK=[CLK:73] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:1] [RAM:73]
  • RAMMODE=[SRL16:35] [SRL32:38]
 OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:1]
 OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:1]
  • OUTFFTYPE=[FF:1]
  • SRINIT_OQ=[1:1]
  • SRTYPE_OQ=[ASYNC:1]
 RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEB=[REGCEB_INV:0] [REGCEB:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:1] [WEB0_INV:0]
  • WEB1=[WEB1:1] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:1]
  • WEB3=[WEB3:1] [WEB3_INV:0]
 RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • DATA_WIDTH_A=[18:1]
  • DATA_WIDTH_B=[18:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • EN_RSTRAM_A=[FALSE:1]
  • EN_RSTRAM_B=[FALSE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEB=[REGCEB_INV:0] [REGCEB:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:1] [WEB0_INV:0]
  • WEB1=[WEB1:1] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:1]
  • WEB3=[WEB3:1] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
 RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
 RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • DATA_WIDTH_A=[9:1]
  • DATA_WIDTH_B=[9:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • EN_RSTRAM_A=[FALSE:1]
  • EN_RSTRAM_B=[FALSE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
 REG_SR
  • CK=[CK:24] [CK_INV:0]
  • LATCH_OR_FF=[FF:24]
  • SRINIT=[SRINIT0:23] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:24]
 SLICEL
  • CLK=[CLK:23] [CLK_INV:0]
 SLICEM
  • CLK=[CLK:32] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:9] [CLK_INV:0]
 
Pin Data
BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
 BSCAN_BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
 BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=4
  • CO3=4
  • CYINIT=1
  • DI0=5
  • DI1=5
  • DI2=4
  • DI3=4
  • O0=5
  • O1=5
  • O2=5
  • O3=4
  • S0=5
  • S1=5
  • S2=5
  • S3=4
 FF_SR
  • CK=1
  • D=1
  • Q=1
  • SR=1
 HARD0
  • 0=1
 HARD1
  • 1=10
 ILOGIC2
  • CLK0=1
  • D=1
  • Q4=1
  • SR=1
 ILOGIC2_IFF
  • CLK0=1
  • D=1
  • Q1=1
  • SR=1
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=3
  • O=2
  • PAD=5
 IOB_IMUX
  • I=2
  • I_B=1
  • OUT=3
 IOB_INBUF
  • OUT=3
  • PAD=3
 IOB_OUTBUF
  • IN=2
  • OUT=2
 LUT5
  • A1=2
  • A2=1
  • A3=2
  • A4=1
  • A5=2
  • O5=20
 LUT6
  • A1=10
  • A2=11
  • A3=13
  • A4=13
  • A5=52
  • A6=54
  • O6=54
 LUT_OR_MEM5
  • A1=23
  • A2=23
  • A3=23
  • A4=23
  • A5=23
  • CLK=23
  • DI1=23
  • O5=23
  • WE=23
 LUT_OR_MEM6
  • A1=73
  • A2=73
  • A3=74
  • A4=74
  • A5=74
  • A6=74
  • CLK=73
  • DI1=38
  • DI2=35
  • MC31=57
  • O6=74
  • WE=73
 OLOGIC2
  • CLK0=1
  • D1=1
  • OQ=1
  • SR=1
 OLOGIC2_OUTFF
  • CK0=1
  • D1=1
  • Q=1
  • SR=1
 PAD
  • PAD=5
 RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=1
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=1
  • DIA30=1
  • DIA31=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • ENB=1
  • REGCEA=1
  • REGCEB=1
  • RSTA=1
  • RSTB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
 RAMB16BWER_RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=1
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=1
  • DIA30=1
  • DIA31=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • ENB=1
  • REGCEA=1
  • REGCEB=1
  • RSTA=1
  • RSTB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
 RAMB8BWER
  • ADDRAWRADDR0=1
  • ADDRAWRADDR1=1
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR2=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR0=1
  • ADDRBRDADDR1=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR2=1
  • ADDRBRDADDR3=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • DOADO4=1
  • DOADO5=1
  • DOADO6=1
  • DOADO7=1
  • DOPADOP0=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
 RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR0=1
  • ADDRAWRADDR1=1
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR2=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR0=1
  • ADDRBRDADDR1=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR2=1
  • ADDRBRDADDR3=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • DOADO4=1
  • DOADO5=1
  • DOADO6=1
  • DOADO7=1
  • DOPADOP0=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
 REG_SR
  • CE=3
  • CK=24
  • D=24
  • Q=24
  • SR=24
 SELMUX2_1
  • 0=1
  • OUT=1
  • S0=1
 SLICEL
  • A5=5
  • A6=5
  • AMUX=5
  • B5=5
  • B6=5
  • BMUX=5
  • C5=4
  • C6=5
  • CIN=4
  • CMUX=5
  • COUT=4
  • D5=4
  • D6=4
  • DMUX=4
 SLICEM
  • A=17
  • A1=32
  • A2=32
  • A3=32
  • A4=32
  • A5=32
  • A6=32
  • AI=20
  • AMUX=7
  • AQ=4
  • AX=12
  • B=1
  • B1=15
  • B2=15
  • B3=15
  • B4=15
  • B5=15
  • B6=15
  • BI=3
  • BMUX=4
  • BQ=3
  • BX=9
  • C=2
  • C1=14
  • C2=14
  • C3=14
  • C4=14
  • C5=14
  • C6=13
  • CE=32
  • CI=4
  • CIN=2
  • CLK=32
  • CMUX=3
  • COUT=6
  • CQ=3
  • CX=8
  • D=3
  • D1=13
  • D2=13
  • D3=14
  • D4=14
  • D5=14
  • D6=14
  • DI=8
  • DMUX=28
  • DQ=3
  • DX=10
 SLICEX
  • A=4
  • A1=5
  • A2=6
  • A3=6
  • A4=6
  • A5=11
  • A6=11
  • AMUX=1
  • AQ=8
  • AX=1
  • B=5
  • B1=4
  • B2=4
  • B3=4
  • B4=4
  • B5=9
  • B6=9
  • BQ=4
  • C=1
  • C1=1
  • C2=1
  • C3=2
  • C4=2
  • C5=7
  • C6=7
  • CE=3
  • CLK=9
  • CMUX=1
  • CQ=6
  • D=3
  • D1=1
  • D2=1
  • D3=1
  • D4=1
  • D5=7
  • D6=8
  • DQ=6
  • SR=9
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-ftg256-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 207 196 0 0 0 0 0
bitgen 76 76 0 0 0 0 0
bitinit 1 1 0 0 0 0 0
cse_server 41 38 0 0 0 0 0
edif2ngd 3 3 0 0 0 0 0
elfcheck 1 1 0 0 0 0 0
libgen 1 1 0 0 0 0 0
map 99 76 0 0 0 0 0
netgen 2 2 0 0 0 0 0
ngcbuild 109 109 0 0 0 0 0
ngdbuild 104 104 0 0 0 0 0
par 76 76 0 0 0 0 0
platgen 7 6 0 0 0 0 0
psf2Edward 1 1 0 0 0 0 0
trce 74 74 0 0 0 0 0
xdsgen 1 1 0 0 0 0 0
xps 17 9 0 0 0 0 0
xst 117 114 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store non-default values only
PROP_SelectedInstanceHierarchicalPath=/Key_Jitter_TB PROP_Simulator=Modelsim-SE Verilog
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2015-08-12T19:52:14 PROP_intWbtProjectID=72D2288FF593401FB51458250AE82308
PROP_intWbtProjectIteration=10 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.Key_Jitter_TB
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=ftg256 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-2 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_INV=1 NGDBUILD_NUM_OBUF=2
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_OBUF=2
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-2-ftg256
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5