led_top Project Status
Project File: led.xise Parser Errors: No Errors
Module Name: led_top Implementation State: Programming File Generated
Target Device: xc6slx25-2ftg256
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
6 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 28 30,064 1%  
    Number used as Flip Flops 28      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 65 15,032 1%  
    Number used as logic 64 15,032 1%  
        Number using O6 output only 36      
        Number using O5 output only 24      
        Number using O5 and O6 4      
        Number used as ROM 0      
    Number used as Memory 0 3,664 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 20 3,758 1%  
Number of MUXCYs used 36 7,516 1%  
Number of LUT Flip Flop pairs used 65      
    Number with an unused Flip Flop 37 65 56%  
    Number with an unused LUT 0 65 0%  
    Number of fully used LUT-FF pairs 28 65 43%  
    Number of unique control sets 1      
    Number of slice register sites lost
        to control set restrictions
4 30,064 1%  
Number of bonded IOBs 4 186 2%  
    Number of LOCed IOBs 4 4 100%  
Number of RAMB16BWERs 0 52 0%  
Number of RAMB8BWERs 0 104 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 272 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 272 0%  
Number of OLOGIC2/OSERDES2s 0 272 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 160 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 38 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.49      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Nov 14 06:19:40 201906 Warnings (0 new)0
Translation ReportCurrentThu Nov 14 06:19:54 2019000
Map ReportCurrentThu Nov 14 06:20:20 2019006 Infos (0 new)
Place and Route ReportCurrentThu Nov 14 06:20:40 2019003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Nov 14 06:20:53 2019004 Infos (0 new)
Bitgen ReportCurrentThu Nov 14 06:21:12 2019000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateThu Oct 20 20:23:10 2016
WebTalk Log FileCurrentThu Nov 14 06:21:14 2019

Date Generated: 11/14/2019 - 06:31:44