#Build: Synplify Pro 9.4A1, Build 169R, Jun 11 2008 #install: D:\actel_sw\Libero84\Libero_v8.4\Synplify\synplify_94A1 #OS: Windows XP 5.1 #Hostname: WXPL-ALEXANDER #Implementation: synthesis #Mon Nov 24 11:35:35 2008 $ Start of Compile #Mon Nov 24 11:35:35 2008 Synplicity VHDL Compiler, version 1.0, Build 061R, built Jun 30 2008 Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns Top entity isn't set yet! VHDL syntax check successful! File D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revA\Igloo_nano_tutorial_design_revB\smartgen\pll1\pll1.vhd changed - recompiling File D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revA\Igloo_nano_tutorial_design_revB\smartgen\counter1\counter1.vhd changed - recompiling File D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revA\Igloo_nano_tutorial_design_revB\smartgen\counter2\counter2.vhd changed - recompiling File D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revA\Igloo_nano_tutorial_design_revB\hdl\top.vhd changed - recompiling File D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revA\Igloo_nano_tutorial_design_revB\smartgen\pll1\pll1.vhd changed - recompiling File D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revA\Igloo_nano_tutorial_design_revB\smartgen\counter1\counter1.vhd changed - recompiling File D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revA\Igloo_nano_tutorial_design_revB\smartgen\counter2\counter2.vhd changed - recompiling File D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revA\Igloo_nano_tutorial_design_revB\hdl\top.vhd changed - recompiling @N:CD630 : top.vhd(8) | Synthesizing work.top.def_arch @W:CD280 : top.vhd(15) | Unbound component INBUF_FF mapped to black box @W:CD326 : top.vhd(51) | Port y of entity work.inbuf_ff is unconnected @N:CD630 : top.vhd(15) | Synthesizing work.inbuf_ff.syn_black_box Post processing for work.inbuf_ff.syn_black_box @N:CD630 : counter2.vhd(8) | Synthesizing work.counter2.def_arch @N:CD630 : igloo.vhd(37) | Synthesizing igloo.and3.syn_black_box Post processing for igloo.and3.syn_black_box @N:CD630 : igloo.vhd(1934) | Synthesizing igloo.inv.syn_black_box Post processing for igloo.inv.syn_black_box @N:CD630 : igloo.vhd(1388) | Synthesizing igloo.dfn1c0.syn_black_box Post processing for igloo.dfn1c0.syn_black_box @N:CD630 : igloo.vhd(2817) | Synthesizing igloo.xor2.syn_black_box Post processing for igloo.xor2.syn_black_box @N:CD630 : igloo.vhd(13) | Synthesizing igloo.and2.syn_black_box Post processing for igloo.and2.syn_black_box @N:CD630 : igloo.vhd(1472) | Synthesizing igloo.dfn1e1c0.syn_black_box Post processing for igloo.dfn1e1c0.syn_black_box Post processing for work.counter2.def_arch @W:CL168 : counter2.vhd(99) | Pruning instance U_AND3_0_1_2 - not in use ... @W:CL168 : counter2.vhd(83) | Pruning instance U_AND2_0_1 - not in use ... @N:CD630 : counter1.vhd(8) | Synthesizing work.counter1.def_arch Post processing for work.counter1.def_arch @W:CL168 : counter1.vhd(283) | Pruning instance U_AND3_15_16_17 - not in use ... @W:CL168 : counter1.vhd(280) | Pruning instance U_AND2_3_4 - not in use ... @W:CL168 : counter1.vhd(269) | Pruning instance U_U_AND3_9_to_17 - not in use ... @W:CL168 : counter1.vhd(116) | Pruning instance U_AND2_9_10 - not in use ... @W:CL168 : counter1.vhd(103) | Pruning instance U_AND2_0_1 - not in use ... @N:CD630 : pll1.vhd(8) | Synthesizing work.pll1.def_arch @N:CD630 : igloo.vhd(3473) | Synthesizing igloo.pll.syn_black_box Post processing for igloo.pll.syn_black_box @N:CD630 : igloo.vhd(406) | Synthesizing igloo.pllint.syn_black_box Post processing for igloo.pllint.syn_black_box @N:CD630 : igloo.vhd(1787) | Synthesizing igloo.gnd.syn_black_box Post processing for igloo.gnd.syn_black_box @N:CD630 : igloo.vhd(2722) | Synthesizing igloo.vcc.syn_black_box Post processing for igloo.vcc.syn_black_box Post processing for work.pll1.def_arch Post processing for work.top.def_arch @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Nov 24 11:35:36 2008 ###########################################################] Synplicity Proasic Technology Mapper, Version 9.4.0, Build 055R, Built Jul 2 2008 07:11:59 Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved Product Version Version 9.4A1 @W:BN246 : | Failed to find top level module 'work.top' as specified in project file @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Automatic dissolve at startup in view:work.top(def_arch) of counter2_1(counter2) Automatic dissolve at startup in view:work.top(def_arch) of counter1_1(counter1) Automatic dissolve at startup in view:work.top(def_arch) of pll1_1(pll1) Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 87MB) Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 87MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 87MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 87MB) Writing Analyst data base D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revB\Igloo_nano_tutorial_design_revB\synthesis\top.srm @N:BN225 : | Writing default property annotation file D:\Apps\Documentation\libero_tutorial_designs\Igloo_nano_tutorial_design_revB\Igloo_nano_tutorial_design_revB\synthesis\top.map. Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 87MB) Writing EDIF Netlist and constraint files Version 9.4A1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 87MB) Found clock top|pll1_1.tb_gla_inferred_clock with period 10.00ns Found clock top|counter1_1.tb_q_inferred_clock[17] with period 10.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Nov 24 11:35:43 2008 # Top view: top Library name: IGLOO_V2 Operating conditions: COMWCSTD ( T = 70.0, V = 1.14, P = 3.70, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: igloo Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -10.848 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------- top|counter1_1.tb_q_inferred_clock[17] 100.0 MHz 91.4 MHz 10.000 10.942 -0.942 inferred Inferred_clkgroup_0 top|pll1_1.tb_gla_inferred_clock 100.0 MHz 48.0 MHz 10.000 20.848 -10.848 inferred Inferred_clkgroup_1 =============================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ top|counter1_1.tb_q_inferred_clock[17] top|counter1_1.tb_q_inferred_clock[17] | 10.000 -0.942 | No paths - | No paths - | No paths - top|pll1_1.tb_gla_inferred_clock top|pll1_1.tb_gla_inferred_clock | 10.000 -10.848 | No paths - | No paths - | No paths - ======================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: top|counter1_1.tb_q_inferred_clock[17] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------- counter2_1.DFN1C0_NU_0 top|counter1_1.tb_q_inferred_clock[17] DFN1C0 Q q_c[0] 1.771 -0.942 counter2_1.DFN1E1C0_NU_1 top|counter1_1.tb_q_inferred_clock[17] DFN1E1C0 Q q_c[1] 1.771 -0.307 counter2_1.DFN1C0_NU_2 top|counter1_1.tb_q_inferred_clock[17] DFN1C0 Q q_c[2] 1.771 4.061 ========================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- counter2_1.DFN1C0_NU_2 top|counter1_1.tb_q_inferred_clock[17] DFN1C0 D XOR2_0_Y 8.705 -0.942 counter2_1.DFN1C0_NU_0 top|counter1_1.tb_q_inferred_clock[17] DFN1C0 D INV_1_Y 8.705 2.099 counter2_1.DFN1E1C0_NU_1 top|counter1_1.tb_q_inferred_clock[17] DFN1E1C0 D INV_0_Y 8.705 3.005 counter2_1.DFN1E1C0_NU_1 top|counter1_1.tb_q_inferred_clock[17] DFN1E1C0 E q_c[0] 8.538 3.924 ============================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 9.647 = Slack (non-critical) : -0.942 Number of logic level(s): 2 Starting point: counter2_1.DFN1C0_NU_0 / Q Ending point: counter2_1.DFN1C0_NU_2 / D The start point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK The end point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- counter2_1.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - q_c[0] Net - - 2.844 - 4 counter2_1.AND2_0 AND2 A In - 4.615 - counter2_1.AND2_0 AND2 Y Out 1.236 5.851 - AND2_0_Y Net - - 0.773 - 1 counter2_1.XOR2_0 XOR2 B In - 6.624 - counter2_1.XOR2_0 XOR2 Y Out 2.251 8.875 - XOR2_0_Y Net - - 0.773 - 1 counter2_1.DFN1C0_NU_2 DFN1C0 D In - 9.647 - ======================================================================================= Total path delay (propagation time + setup) of 10.942 is 6.553(59.9%) logic and 4.389(40.1%) route. Path information for path number 2: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 9.012 = Slack (non-critical) : -0.307 Number of logic level(s): 2 Starting point: counter2_1.DFN1E1C0_NU_1 / Q Ending point: counter2_1.DFN1C0_NU_2 / D The start point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK The end point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- counter2_1.DFN1E1C0_NU_1 DFN1E1C0 Q Out 1.771 1.771 - q_c[1] Net - - 1.938 - 3 counter2_1.AND2_0 AND2 B In - 3.708 - counter2_1.AND2_0 AND2 Y Out 1.508 5.216 - AND2_0_Y Net - - 0.773 - 1 counter2_1.XOR2_0 XOR2 B In - 5.989 - counter2_1.XOR2_0 XOR2 Y Out 2.251 8.240 - XOR2_0_Y Net - - 0.773 - 1 counter2_1.DFN1C0_NU_2 DFN1C0 D In - 9.012 - =========================================================================================== Total path delay (propagation time + setup) of 10.307 is 6.824(66.2%) logic and 3.483(33.8%) route. Path information for path number 3: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 6.607 = Slack (non-critical) : 2.099 Number of logic level(s): 1 Starting point: counter2_1.DFN1C0_NU_0 / Q Ending point: counter2_1.DFN1C0_NU_0 / D The start point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK The end point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- counter2_1.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - q_c[0] Net - - 2.844 - 4 counter2_1.INV_1 INV A In - 4.615 - counter2_1.INV_1 INV Y Out 1.219 5.834 - INV_1_Y Net - - 0.773 - 1 counter2_1.DFN1C0_NU_0 DFN1C0 D In - 6.607 - ======================================================================================= Total path delay (propagation time + setup) of 7.901 is 4.285(54.2%) logic and 3.617(45.8%) route. Path information for path number 4: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 5.700 = Slack (non-critical) : 3.005 Number of logic level(s): 1 Starting point: counter2_1.DFN1E1C0_NU_1 / Q Ending point: counter2_1.DFN1E1C0_NU_1 / D The start point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK The end point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- counter2_1.DFN1E1C0_NU_1 DFN1E1C0 Q Out 1.771 1.771 - q_c[1] Net - - 1.938 - 3 counter2_1.INV_0 INV A In - 3.708 - counter2_1.INV_0 INV Y Out 1.219 4.928 - INV_0_Y Net - - 0.773 - 1 counter2_1.DFN1E1C0_NU_1 DFN1E1C0 D In - 5.700 - =========================================================================================== Total path delay (propagation time + setup) of 6.995 is 4.285(61.3%) logic and 2.710(38.7%) route. Path information for path number 5: Requested Period: 10.000 - Setup time: 1.462 = Required time: 8.538 - Propagation time: 4.615 = Slack (non-critical) : 3.923 Number of logic level(s): 0 Starting point: counter2_1.DFN1C0_NU_0 / Q Ending point: counter2_1.DFN1E1C0_NU_1 / E The start point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK The end point is clocked by top|counter1_1.tb_q_inferred_clock[17] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- counter2_1.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - q_c[0] Net - - 2.844 - 4 counter2_1.DFN1E1C0_NU_1 DFN1E1C0 E In - 4.615 - =========================================================================================== Total path delay (propagation time + setup) of 6.077 is 3.232(53.2%) logic and 2.844(46.8%) route. ==================================== Detailed Report for Clock: top|pll1_1.tb_gla_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------ counter1_1.DFN1C0_NU_0 top|pll1_1.tb_gla_inferred_clock DFN1C0 Q tb_q[0] 1.771 -10.848 counter1_1.DFN1E1C0_NU_3 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 Q tb_q[3] 1.771 -10.368 counter1_1.DFN1E1C0_NU_1 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 Q tb_q[1] 1.771 -10.284 counter1_1.DFN1E1C0_NU_4 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 Q tb_q[4] 1.771 -9.804 counter1_1.DFN1C0_NU_2 top|pll1_1.tb_gla_inferred_clock DFN1C0 Q tb_q[2] 1.771 -9.357 counter1_1.DFN1E1C0_NU_5 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 Q tb_q[5] 1.771 -8.877 counter1_1.DFN1C0_NU_6 top|pll1_1.tb_gla_inferred_clock DFN1C0 Q tb_q[6] 1.771 -8.380 counter1_1.DFN1E1C0_NU_7 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 Q tb_q[7] 1.771 -7.816 counter1_1.DFN1E1C0_NU_9 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 Q tb_q[9] 1.771 -7.565 counter1_1.DFN1E1C0_NU_10 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 Q tb_q[10] 1.771 -7.002 ======================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------- counter1_1.DFN1E1C0_NU_16 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 D XOR2_12_Y 8.705 -10.848 counter1_1.DFN1E1C0_NU_17 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 D XOR2_8_Y 8.705 -10.848 counter1_1.DFN1E1C0_NU_9 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -5.983 counter1_1.DFN1E1C0_NU_10 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -5.983 counter1_1.DFN1E1C0_NU_11 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -5.983 counter1_1.DFN1E1C0_NU_12 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -5.983 counter1_1.DFN1E1C0_NU_13 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -5.983 counter1_1.DFN1E1C0_NU_14 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -5.983 counter1_1.DFN1E1C0_NU_15 top|pll1_1.tb_gla_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -5.983 counter1_1.DFN1C0_NU_6 top|pll1_1.tb_gla_inferred_clock DFN1C0 D XOR2_10_Y 8.705 -5.724 ========================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 19.553 = Slack (critical) : -10.848 Number of logic level(s): 4 Starting point: counter1_1.DFN1C0_NU_0 / Q Ending point: counter1_1.DFN1E1C0_NU_16 / D The start point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK The end point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- counter1_1.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - tb_q[0] Net - - 2.844 - 4 counter1_1.U_AND3_0_1_2 AND3 A In - 4.615 - counter1_1.U_AND3_0_1_2 AND3 Y Out 1.115 5.730 - NU_0_1_2 Net - - 3.667 - 7 counter1_1.U_U_AND3_0_to_8 AND3 A In - 9.397 - counter1_1.U_U_AND3_0_to_8 AND3 Y Out 1.115 10.512 - NU_0_to_8 Net - - 4.009 - 9 counter1_1.AND2_0 AND2 A In - 14.521 - counter1_1.AND2_0 AND2 Y Out 1.236 15.757 - AND2_0_Y Net - - 0.773 - 1 counter1_1.XOR2_12 XOR2 B In - 16.530 - counter1_1.XOR2_12 XOR2 Y Out 2.251 18.781 - XOR2_12_Y Net - - 0.773 - 1 counter1_1.DFN1E1C0_NU_16 DFN1E1C0 D In - 19.553 - ============================================================================================= Total path delay (propagation time + setup) of 20.848 is 8.783(42.1%) logic and 12.065(57.9%) route. Path information for path number 2: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 19.553 = Slack (critical) : -10.848 Number of logic level(s): 4 Starting point: counter1_1.DFN1C0_NU_0 / Q Ending point: counter1_1.DFN1E1C0_NU_17 / D The start point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK The end point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- counter1_1.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - tb_q[0] Net - - 2.844 - 4 counter1_1.U_AND3_0_1_2 AND3 A In - 4.615 - counter1_1.U_AND3_0_1_2 AND3 Y Out 1.115 5.730 - NU_0_1_2 Net - - 3.667 - 7 counter1_1.U_U_AND3_0_to_8 AND3 A In - 9.397 - counter1_1.U_U_AND3_0_to_8 AND3 Y Out 1.115 10.512 - NU_0_to_8 Net - - 4.009 - 9 counter1_1.AND2_10 AND2 A In - 14.521 - counter1_1.AND2_10 AND2 Y Out 1.236 15.757 - AND2_10_Y Net - - 0.773 - 1 counter1_1.XOR2_8 XOR2 B In - 16.530 - counter1_1.XOR2_8 XOR2 Y Out 2.251 18.781 - XOR2_8_Y Net - - 0.773 - 1 counter1_1.DFN1E1C0_NU_17 DFN1E1C0 D In - 19.553 - ============================================================================================= Total path delay (propagation time + setup) of 20.848 is 8.783(42.1%) logic and 12.065(57.9%) route. Path information for path number 3: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 19.073 = Slack (non-critical) : -10.368 Number of logic level(s): 4 Starting point: counter1_1.DFN1E1C0_NU_3 / Q Ending point: counter1_1.DFN1E1C0_NU_16 / D The start point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK The end point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- counter1_1.DFN1E1C0_NU_3 DFN1E1C0 Q Out 1.771 1.771 - tb_q[3] Net - - 2.844 - 4 counter1_1.U_AND3_3_4_5 AND3 A In - 4.615 - counter1_1.U_AND3_3_4_5 AND3 Y Out 1.115 5.730 - NU_3_4_5 Net - - 2.844 - 4 counter1_1.U_U_AND3_0_to_8 AND3 B In - 8.574 - counter1_1.U_U_AND3_0_to_8 AND3 Y Out 1.458 10.031 - NU_0_to_8 Net - - 4.009 - 9 counter1_1.AND2_0 AND2 A In - 14.041 - counter1_1.AND2_0 AND2 Y Out 1.236 15.277 - AND2_0_Y Net - - 0.773 - 1 counter1_1.XOR2_12 XOR2 B In - 16.049 - counter1_1.XOR2_12 XOR2 Y Out 2.251 18.301 - XOR2_12_Y Net - - 0.773 - 1 counter1_1.DFN1E1C0_NU_16 DFN1E1C0 D In - 19.073 - ============================================================================================= Total path delay (propagation time + setup) of 20.368 is 9.125(44.8%) logic and 11.243(55.2%) route. Path information for path number 4: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 19.073 = Slack (non-critical) : -10.368 Number of logic level(s): 4 Starting point: counter1_1.DFN1E1C0_NU_3 / Q Ending point: counter1_1.DFN1E1C0_NU_17 / D The start point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK The end point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- counter1_1.DFN1E1C0_NU_3 DFN1E1C0 Q Out 1.771 1.771 - tb_q[3] Net - - 2.844 - 4 counter1_1.U_AND3_3_4_5 AND3 A In - 4.615 - counter1_1.U_AND3_3_4_5 AND3 Y Out 1.115 5.730 - NU_3_4_5 Net - - 2.844 - 4 counter1_1.U_U_AND3_0_to_8 AND3 B In - 8.574 - counter1_1.U_U_AND3_0_to_8 AND3 Y Out 1.458 10.031 - NU_0_to_8 Net - - 4.009 - 9 counter1_1.AND2_10 AND2 A In - 14.041 - counter1_1.AND2_10 AND2 Y Out 1.236 15.277 - AND2_10_Y Net - - 0.773 - 1 counter1_1.XOR2_8 XOR2 B In - 16.049 - counter1_1.XOR2_8 XOR2 Y Out 2.251 18.301 - XOR2_8_Y Net - - 0.773 - 1 counter1_1.DFN1E1C0_NU_17 DFN1E1C0 D In - 19.073 - ============================================================================================= Total path delay (propagation time + setup) of 20.368 is 9.125(44.8%) logic and 11.243(55.2%) route. Path information for path number 5: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 18.990 = Slack (non-critical) : -10.284 Number of logic level(s): 4 Starting point: counter1_1.DFN1E1C0_NU_1 / Q Ending point: counter1_1.DFN1E1C0_NU_16 / D The start point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK The end point is clocked by top|pll1_1.tb_gla_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- counter1_1.DFN1E1C0_NU_1 DFN1E1C0 Q Out 1.771 1.771 - tb_q[1] Net - - 1.938 - 3 counter1_1.U_AND3_0_1_2 AND3 B In - 3.708 - counter1_1.U_AND3_0_1_2 AND3 Y Out 1.458 5.166 - NU_0_1_2 Net - - 3.667 - 7 counter1_1.U_U_AND3_0_to_8 AND3 A In - 8.833 - counter1_1.U_U_AND3_0_to_8 AND3 Y Out 1.115 9.948 - NU_0_to_8 Net - - 4.009 - 9 counter1_1.AND2_0 AND2 A In - 13.957 - counter1_1.AND2_0 AND2 Y Out 1.236 15.193 - AND2_0_Y Net - - 0.773 - 1 counter1_1.XOR2_12 XOR2 B In - 15.966 - counter1_1.XOR2_12 XOR2 Y Out 2.251 18.217 - XOR2_12_Y Net - - 0.773 - 1 counter1_1.DFN1E1C0_NU_16 DFN1E1C0 D In - 18.990 - ============================================================================================= Total path delay (propagation time + setup) of 20.284 is 9.125(45.0%) logic and 11.159(55.0%) route. ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Report for cell top.def_arch Core Cell usage: cell count area count*area AND2 16 1.0 16.0 AND3 6 1.0 6.0 GND 4 0.0 0.0 INV 6 1.0 6.0 NOR2B 1 1.0 1.0 PLL 1 0.0 0.0 PLLINT 1 0.0 0.0 VCC 4 0.0 0.0 XOR2 15 1.0 15.0 DFN1C0 5 1.0 5.0 DFN1E1C0 16 1.0 16.0 ----- ---------- TOTAL 75 65.0 IO Cell usage: cell count INBUF 2 INBUF_FF 1 OUTBUF 3 ----- TOTAL 6 Core Cells : 65 of 6144 (1%) IO Cells : 6 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Mon Nov 24 11:35:43 2008 ###########################################################]